TL;DR
Developers have showcased a version of the Project Oberon system running on RISC-V processors, shifting from the original RISC-5 architecture. This development signals potential for broader hardware support and modernization of the system.
A version of the Project Oberon system has been successfully ported to run on RISC-V hardware, replacing the original RISC-5 platform, according to a recent Show HN post. This development demonstrates the system’s adaptability to modern open-source processor architectures and could influence future educational and research projects based on Oberon.
The port was showcased by a developer who shared the progress on Show HN, highlighting that the core Oberon system, originally designed for the RISC-5 architecture, has been adapted to run on RISC-V processors. The effort involved significant modifications to the system’s bootloader, kernel, and hardware interface layers to support RISC-V’s specifications.
While the project is still in early testing stages, the developer confirmed that basic functionality, including the graphical interface and file system, has been achieved on RISC-V hardware. The port aims to preserve Oberon’s simplicity and educational value while leveraging the open-source and flexible nature of RISC-V.
It is important to note that this development is currently a proof of concept shared publicly without official backing from the original Oberon creators or hardware manufacturers. The project’s status and future support remain uncertain.
Implications for Open-Source Hardware and Education
This porting effort demonstrates that the Project Oberon system can be adapted to modern, open-source hardware architectures, broadening its potential use in educational settings and research. RISC-V’s open design allows for customization and experimentation, which could foster new developments in operating system design, hardware-software integration, and minimalistic computing environments.
Furthermore, this effort could encourage similar projects to explore porting legacy or research operating systems to RISC-V, contributing to a diverse open hardware ecosystem. For students and developers, Oberon’s simplicity combined with RISC-V’s flexibility provides a practical platform for learning and experimentation.
XIAO ESP32C3 3PCS Pack – RISC-V Tiny MCU Board with Wi-Fi and Bluetooth5.0, Battery Charge Supported, Power Efficiency and Rich Interface
- MCU Chip: ESP32-C3 RISC-V 32-bit, up to 160 MHz
- Development Compatibility: Supports Arduino, MicroPython, PlatformIO, and more
- Wireless Connectivity: Wi-Fi and Bluetooth 5.0 with 100m range
As an affiliate, we earn on qualifying purchases.
As an affiliate, we earn on qualifying purchases.
Background of Project Oberon and RISC-V Compatibility Challenges
Project Oberon, developed by Niklaus Wirth and colleagues at ETH Zurich in the late 1980s, is a minimalist operating system and programming environment designed primarily for educational use. It was originally built for hardware platforms like RISC-5, which was used in early Oberon systems.
RISC-V, an open-source instruction set architecture, has gained popularity due to its modular design and community-driven development. Porting Oberon to RISC-V involves technical challenges such as adapting low-level hardware interfaces, boot processes, and device drivers. The recent Show HN post indicates progress in addressing these issues, though full compatibility and stability are still in development.
This project represents a notable step in porting legacy operating systems to RISC-V, with limited prior public information on similar efforts.
“This is an early proof of concept, but it shows that Oberon can run on modern open hardware like RISC-V. We’re still ironing out some issues, but the core system is operational.”
— the developer behind the port
RISC-V FOR EMBEDDED SYSTEMS: THE COMPLETE DEVELOPMENT GUIDE: Build IoT, Automotive, Edge Devices with Open-Source Processors. Microcontrollers, Real-Time OS, AI Acceleration and Production Deployment
As an affiliate, we earn on qualifying purchases.
As an affiliate, we earn on qualifying purchases.
Unconfirmed Aspects of System Stability and Future Support
The stability and long-term support for the RISC-V port are still uncertain. The project remains in early development, with ongoing work needed to ensure compatibility across different RISC-V implementations and peripherals. The original Oberon developers have not publicly endorsed this port, and future development plans are unclear.
Project Oberon: The Design of an Operating System and Compiler (Acm Press Books)
As an affiliate, we earn on qualifying purchases.
As an affiliate, we earn on qualifying purchases.
Next Steps in RISC-V Oberon Development and Testing
The developer plans to improve stability, add features, and test on various RISC-V hardware platforms. Community involvement could lead to more formal support or integration into educational tools. Updates will be shared through forums and the original Show HN post as progress continues.
fanxiang 500GB NVMe SSD PCIe Gen 4 Gaming SSD for PS5, Up to 6300MB/s M.2 2280 SSD Compatible with PS5 Storage Expansion, Internal Solid State Drive for Gamers, Professionals, Creators S880E
- Extreme PCIe 4.0 Performance: Up to 6300MB/s read speed
- Optimized for Gaming: Compatible with PS5 and DirectStorage
- High-Speed Data Transfer: Fast boot, load, and file processing
As an affiliate, we earn on qualifying purchases.
As an affiliate, we earn on qualifying purchases.
Key Questions
What is Project Oberon?
Project Oberon is a minimalist operating system and programming environment developed at ETH Zurich, primarily for educational purposes and research.
Why is porting Oberon to RISC-V important?
Porting Oberon to RISC-V demonstrates its adaptability to modern open-source hardware, which could expand its use in education, research, and minimalistic OS development.
Is this port officially supported by the original Oberon creators?
No, this is an independent, early-stage port shared publicly without official endorsement or backing from the original developers.
What technical challenges are involved in this port?
Challenges include adapting hardware interfaces, modifying the bootloader, and supporting device drivers to match RISC-V specifications.
Will this port become a stable release?
It is in early testing; additional development is needed before it can be considered stable or ready for widespread use.
Source: hn
